(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for fabricating an array of memory cells for dynamic random access memory (DRAM) devices with increased capacitance using a simple process. This new process provides an essentially planar surface over the total surface of the DRAM chip (device). This eliminates a chemical/mechanical polishing (CMP) step that would otherwise be required to provide a planar topography across the DRAM chip.
(2) Description of the Prior Art
The integrated circuit density on chips formed from semiconductor substrates has dramatically increased in recent years. The increase in density is the result of down scaling of the individual semiconductor devices built in and on the substrate. Typically the semiconductor devices are formed from patterned polysilicon layers and doped regions in the substrate, and the interconnect for these individual devices are formed from multilayers of patterning conducting layers, such as doped polysilicon and metal layers with interposed insulating layers. Typically the layers are patterned using high resolution photolithographic techniques and directional etching, such as High Density Plasma (HDP) etching. Unfortunately, as the device feature size decrease to submicrometer dimensions it is necessary to provide a planar surface across the chip for the shallow Depth Of Focus (DOF) needed to expose and develop the high fidelity distortion free images in the overlying photoresist layers. Also the planar surface is necessary to reliably pattern the various material layers used in the fabrication of integrate circuits on the semiconductor substrate when directional plasma etching is use to make submicrometer patterns. For example, when patterning a metal layer to make electrical interconnections over a surface with a rough topography can result in residual metal remaining on the sidewall in recess on the rough surface which can then lead to intralevel shorts between metal lines.
One circuit type experiencing this demand for increased circuit density and the need for an essentially planar surface is the dynamic random access memory (DRAM) chip (or devices) made on a semiconductor substrate and later removed by dicing. The DRAM chip areas on the substrate consist of an array of closely spaced memory cells with address and read/write circuits along the periphery of the chip. Currently in production there are 64 million memory cells on a DRAM chip with minimum features sizes less than a half micrometer. The individual memory cells are formed from a single access transistor, typically a field effect transistor (FET), and a storage capacitor with a node contact to one of the two source/drain areas of the FET. The capacitor is used for storing information in binary form (0's and 1's) as electrical charge, and the second source/drain area is connected to a bit line that is used to read and write information via peripheral circuits on the DRAM chip. World lines that also form the FET gate electrodes are used to randomly access (address) the individual memory cells.
Both trench capacitors, formed in the substrate and stacked capacitors, formed on the substrate surface over the FET are currently being pursued for DRAM applications. However, the stacked capacitor has received considerable attention in recent years because of the various ways its shape can be changed in the vertical direction to increase capacitance without increasing the area it occupies on the cell area. However, as the cell density increases and the cell size shrink to accommodate more cells, it is necessary to increase the vertical dimension of the stacked capacitor. This is to provide sufficient capacitance to maintain the necessary charge for acceptable sign-to-noise levels and to provide a reasonable refresh cycle times.
Unfortunately, as the stacked capacitors are increased in height the topography across the chip becomes rougher, and the problem associated with reliably exposing the photoresist and etching high aspect ratio patterns in the material layers are made more difficult. Although the spaces between the closely spaced capacitors in the memory cell area can be easily filled with an insulator to provide a relatively planar surface, the topography at the perimeter of the array cell near the periphery of the chip can be considerably greater than 1.0 micrometer in height.
To better appreciate this topography problem a schematic cross sectional view of a convention Capacitor-Over-Bit line (COB) DRAM structure at the perimeter of the memory cell array is shown in FIG. 1. The structure consist of a semiconductor substrate 10, in and on which are formed field oxide (FOX) regions 12 to isolated the various device areas on the substrate 10. A gate oxide 14 is grown on the device areas for the FET's and a polycide layer 19 (polysilicon 16 and silicide 17) is deposited with a cap oxide 20, and the multilayer is patterned to form the FET gate electrode. Lightly doped source/drain regions 22(N.sup.-) are formed by ion implantation or diffusion followed by depositing an insulating layer and anisotropically etching back to form sidewall spacers 26. The FET heavily doped source/drain contact regions 24(N.sup.+) are then formed by ion implantation in the peripheral area of the DRAM chip, while the memory cell area is masked from implantation to minimize leakage currents. Now in the COB DRAM device (chip), a second polysilicon or polycide layer is deposited and patterned to form the bit lines (not shown in the cross section) and to concurrently form the capacitor node contacts/landing pads 28. An insulating layer 29 is deposited and planarized and node contact openings 2 are etched to the landing pads 28. A thick polysilicon layer 30 is deposited and patterned to form the capacitor bottom electrodes 30 with increased area to provide increased capacitance. However, the patterning of the thick polysilicon requires a thick photoresist mask that further reduces resolution and limits cell density. Other types of stacked capacitor structures can be formed such as cylindrical, fin, crown shaped and the like, but also result in exceptionally rough topography. After forming the bottom electrode 30 a thin interelectrode dielectric layer 32 is formed and another polysilicon layer 34 is deposited and patterned to form the top electrode 34. An insulating layer 36 is then deposited to insulate the capacitors. Unfortunately, the capacitor bottom electrode formed from the thick polysilicon result in a large step having a height H which can be greater than 1.0 um and exacerbate the photoresist image fidelity need to patterned the next layer for integration, such as the via hole 4 and the next level of metal interconnections 38. One conventional method of avoiding this rough topography problem is to deposit a much thicker insulating layer 36 than is shown in FIG. 1 and then chemical/mechanical polishing (CMP) back to globally planarize the surface. However, this additional CMP is costly and can result in substrate damage.
Numerous approaches to making DRAM circuits using COB structures have been reported, but do not address the above rough topography problem, that is the high step at the perimeter of the array of memory cells on the chip. For example, Liaw et al. in U.S. Pat. No. 5,543,345, teaches a method for making crown capacitors, and Koh in U.S. Pat. No. 5,554,557 teaches a method for making stacked capacitors with self-aligned node contacts having an up-ward extending sidewall. Still another method is described by Yun in U.S. Pat. No. 5,389,568, for making Y-shaped capacitors.
There is still a need in the semiconductor industry to provide a simple COB DRAM process having a more planar stacked capacitor structure that eliminates the need for chemical/mechanical polishing, and also avoid the need to etch very thick polysilicon layers.